1. Field of the Invention
The present invention relates to a semiconductor memory device which is at least readable.
2. Description of the Related Art
Recently, there has been a demand for a high-speed microcomputer having an operating speed corresponding to more than 100 MHz. As the operating speed of a microcomputer is increased, a higher operating speed is required for a ROM and flash memory mounted on the same chip on which the microcomputer is mounted. The ROM and flash memory are mounted on a chip typically for the purposes of customization.
Moreover, a memory having a higher capacity is required with an increase in the performance recent microcomputers.
In this situation, a large-capacity semiconductor memory device from which data can be read at a high speed has been researched and developed. For example, Japanese Patent Application No. 11-349301 proposes a semiconductor memory device having a hierarchical bit line architecture. Similarly, Mitsuru Hiraki et al. xe2x80x9cISSCC99/SESSION6/PAPER MP6.8 (A3.3V 90 MHz xe2x80xa2 Flash Memory Module Embedded in a 32b RISC Microcontroller)xe2x80x9d, Feb. 15, 1999, proposes a sense-type semiconductor memory device having a high readout speed.
In the semiconductor memory device disclosed in the above-described publication, both a global bit line (corresponding to a main bit line) and a local bit line (corresponding to a sub-bit line) are discharged to a ground level in advance; a global bit line and local bit line corresponding to a read address is selected; and precharging the selected global and local bit lines is initiated. During the precharging step (before precharge is completed), a sense operation is conducted. As is different from previous techniques, both a global bit line and a local bit line are discharged to a ground level, so that an influence of the potentials of the global and local bit lines in a previous readout operation is eliminated and a sense operation can be carried out during the precharging step.
However, since the rate of precharging is substantially half the cell current, a potential difference between a readout side and a reference side is not present until the current driving performance of a memory cell becomes full, i.e., a local sub-bit line (local bit line) is charged to a certain potential. Therefore, a sense operation can be initiated during a precharging operation only after a local sub-bit line (local bit line) has been charged to a certain potential.
Also, for example, the semiconductor memory device disclosed in Japanese Patent Application No. 11-349301 comprises an information readout section, a reference section, a differential sense amplifier which receives information outputs from the information readout section and the reference section, and a control section which controls each section.
The information readout section has a sub-bit line connected via a selection gate to a main bit line, a plurality of memory cells connected to the sub-bit line, which are selectively activated in response to the voltage of a word line, a precharge section which precharges the main bit line and a main bit line at the input end side of the differential sense amplifier, and a reset section which resets the sub-bit line side to the ground potential.
The control section controls the precharge section so as to achieve high-speed information readout as follows. The main bit line and the main bit line at the input end side of the differential sense amplifier are precharged. The reset section is controlled in a manner that sets the sub-bit line side to the ground potential. Thereafter, a portion of the electric charge precharged at the main bit line and the main bit line at the input end side of the differential sense amplifier is redistributed to the sub-bit line side by controlling the selection gate.
However, in the above-described semiconductor memory device, voltages are not simultaneously applied to gates due to differences in load capacity among a word line, a reference word line, and a selection gate control line (in the case of a non-volatile memory, due to differences in devices due to differences in voltage systems). In the case of a non-volatile memory, a voltage is generally applied to a word line by a driver in a high voltage system. Therefore, once an address has been determined, a word line actually goes high slower than a reference word line and a selection gate. Since a word line, a reference word line, and a selection gate control line do not simultaneously go high, it is difficult to accurately read information from the memory cells.
For example, it is assumed that the reference section side is earlier connected to the input end side of the differential sense amplifier and a flow of reference current begins, while a flow of current occurs later in a cell in which a current inherently flows at the information readout section side. In this case, the reference section side of the main bit line initially has a lower voltage than that of the reference section side thereof, and thereafter, the readout side thereof is lowered, so that the reference section side of the main bit line initially has a higher voltage than that of the readout side thereof. Therefore, when a sense operation is activated, since voltages are not simultaneously applied to a word line and a reference word line, an information read operation is not likely to be performed accurately.
According to one aspect of the present invention, a semiconductor memory device comprises memory cells, reference cells, sub-bit lines, at least the memory cells or the reference cells being connected to the sub-bit lines, a first selection gate, a second selection gate, a main bit line, the sub-bit lines being connected via the first selection gate to the main bit line, complementary sub bit lines, at least the other of the memory cells and the reference cells being connected to the complementary sub-bit line, a complementary main bit line, the complementary sub-bit lines being connected via the second selection gate to the complementary main bit line, word lines corresponding to the memory cells, reference word lines corresponding to the reference cells, a word line driving section for selectively activating at least one of the word lines, a reference word line driving section for selectively activating at least one of the reference word lines, and a control section for outputting a selection gate signal to the first and second selection gates, the selection gate signal activating the first and second selection gates, the time of activating the first and second selection gates being delayed from the time of activating the word lines and the reference word lines to an extent that potential inversion does not occur between the main bit line and the complementary main bit line. Information is read from the memory cells via the main bit line and the complementary main bit line.
With this configuration, until after potential inversion occurs between a main bit line and a complementary main bit line due to a time lag between a word line and a reference word line, the time of activating a selection gate is delayed from the times of activating a word line and a reference word line. Therefore, performance of an accurate sense operation can be secured, so that information can be accurately read from memory cells without error.
In one embodiment of this invention, the semiconductor memory device further comprises a differential sense amplifier comprising first and second input ends, for sensing a difference in voltage between the first and second input ends, a precharge section for precharging the main bit line and the complementary main bit line to a first voltage, and a reset section for resetting the sub-bit lines and the complementary sub-bit lines to a second voltage lower than the first voltage, and releasing the reset state of one of the sub-bit lines and releasing the reset state of one of the complementary sub-bit lines. The main bit line is connected to the first input end, the complementary main bit line is connected to the second input end, the first selection gate selectively connects the main bit line to one of the sub-bit lines, and the second selection gate selectively connects the complementary main bit line to one of the complementary sub-bit lines. The control section controls the differential sense amplifier, the precharge section, the reset section, and the selection gate section so that the main bit line and the complementary main bit line are precharged to the first voltage, the sub-bit lines and the complementary sub-bit lines are reset to the second voltage in advance, and after selectively releasing the reset state of one of the sub-bit lines and one of the complementary sub-bit lines, a portion of electric charge precharged in the main bit line is redistributed to the reset-state released sub-bit line via the first selection gate, and a portion of electric charge in the complementary main bit line is redistributed to the reset-state released complementary sub-bit line via the second selection gate, and thereafter a sense operation is performed.
With this configuration, the selection gate of the present invention can be easily controlled in this array arrangement.
In one embodiment of this invention, the semiconductor memory device further comprises a differential sense amplifier comprising first and second input ends, for sensing a difference in voltage between the first and second input ends, a first separation gate for connecting or disconnecting the first input end and the main bit line, a second separation gate for connecting or disconnecting the second input end and the main bit line, the complementary main bit line being connected via the second separation gate to the second input end, a precharge section for precharging the main bit line and the complementary main bit line to a first voltage, and a reset section for resetting the sub-bit lines and the complementary sub-bit lines to a second voltage lower than the first voltage, and releasing the reset state of one of the sub-bit lines and releasing the reset state of one of the complementary sub-bit lines. The main bit line is connected via the first separation gate to the first input end, the first selection gate selectively connects the main bit line to one of the sub-bit lines, and the second selection gate selectively connects the complementary main bit line to one of the complementary sub-bit lines. The control section controls the precharge section, the reset section, and the selection gate section so that the main bit line and the complementary main bit line are precharged to the first voltage, the sub-bit lines and the complementary sub-bit lines are reset to the second voltage in advance, and after selectively releasing the reset state of one of the sub-bit lines and one of the complementary sub-bit lines, a portion of electric charge precharged in the main bit line is redistributed to the reset-state released sub-bit line via the first selection gate, and a portion of electric charge in the complementary main bit line is redistributed to the reset-state released complementary sub-bit line via the second selection gate, and thereafter a sense operation is performed, and thereafter, at the same time as or immediately after initiating a sense operation of the differential sense amplifier, the control section controls the first separation gate to disconnect the first input end and the main bit line and the second separation gate to disconnect the second input end and the complementary main bit line, and disables the first and second selection gate so that the main bit line and the complementary bit line are precharged, and the sub-bit line and the complementary bit line are discharged.
With this configuration, the differential sense amplifier is separated from the main bit line by the first and second separation gates, so that a sense operation and precharge and discharge operations can be performed in parallel. Therefore, high-speed information reading can be obtained.
In one embodiment of this invention, a plurality of subarrays are arranged in a direction along the main bit line and the complementary main bit line. Each subarray comprises a memory cell array comprising the memory cells, a reference cell array comprising the reference cells, the reset section, and the selection gate section.
With this configuration, the selection gate switching control arrangement of this invention can be easily applied to a semiconductor memory device comprising a plurality of subarrays.
In one embodiment of this invention, at least one of the memory cells and at least one of the reference memory cells are connected to each sub-bit line, and at least one of the memory cells and at least one of the reference memory cells are connected to each complementary sub-bit line.
With this configuration, the selection gate switching control arrangement of this invention can be easily applied to a semiconductor memory device comprising sub-bit lines and complementary sub-bit lines and a plurality of subarrays to which memory cells and reference cells are connected.
In one embodiment of this invention, connecting the main bit line to the sub-bit lines via the first selection gate and connecting the complementary main bit line to the complementary sub-bit lines via the second selection gate are performed in response to a scanning signal for selecting the word lines or an address signal to be decoded to the scanning signal.
With this configuration, the selection gate can be easily controlled in the array arrangement. When the delay time of a signal is determined using a signal (scanning signal) from a system in which a signal is delayed, the time of activating the selection gate is securely delayed from the time of activating the word line.
In one embodiment of this invention, the control section determines the time of activating the differential sense amplifier for a sense operation in response to the scanning signal from the word line driving section or the address signal to be decoded to the scanning signal.
With this configuration, a sense time can be easily and stably determined or adjusted by using a signal output from the selection gate controlled by receiving a scanning signal or an address signal to be decoded to the scanning signal.
In one embodiment of this invention, the first and second selection gates each comprise a first-stage selection gate and a plurality of second-stage selection gates, the first selection gate is provided between the main bit line and the sub-bit lines and the second selection gate is provided between the complementary main bit line and the complementary sub-bit lines, the plurality of second-stage selection gates are hierarchically branched from the first-stage selection gate, and the control section deliberately delays the time of switching on the first-stage selection gate.
With this configuration, when the two-stage selection gates are hierarchically provided, the timing of delay is adjusted in the selection gate at the main bit line side. Before this, it is possible to effectively reset between the first and second selection gates.
In one embodiment of this invention, the first and second selection gates each comprise a first-stage selection gate and a plurality of second-stage selection gates, the first selection gate is provided between the main bit line and the sub-bit lines and the second selection gate is provided between the complementary main bit line and the complementary sub-bit lines, the plurality of second-stage selection gates are hierarchically branched from the first-stage selection gate, and the control section switches on the second-stage selection gates a predetermined time earlier than that of the first-stage selection gate, and after a predetermined time, switches off the first-stage selection gate earlier than that of the second-stage selection gates.
With this configuration, when the two-stage selection gates are hierarchically provided, the selection gate at the main bit line side is earlier closed, and after discharging, the selection gate at the sub-bit line side is cut off.
In one embodiment of this invention, the control section has a canceling section for canceling information reading, and the canceling section prohibits control of switching on the first and second selection gates.
With this configuration, an abort process is prepared so that the selection gate can be canceled at high speed. When information read is canceled partway, a memory operation has to be resumed from a precharge operation, resulting in access penalty. This access penalty when canceling an information read operation is reduced.
Thus, the invention described herein makes possible the advantages of providing a semiconductor memory device in which an accurate sense operation is performed without improper reading of information.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.